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| E2U0038-28-81 Semiconductor MSM7620 Semiconductor Echo Canceler This version: Aug. 1998 MSM7620 Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM7620 is an improved version of the MSM7520 with the same basic configuration. The MSM7620 includes following improvements: a modified through mode, timing control of the control pin input, and a thinner package. The MSM7620 also provides a pin-for-pin replacement with the MSM7520. The MSM7620 is a low-power CMOS IC device for canceling echo (in an acoustic system or telephone line) generated in a speech path. Echo is canceled (in digital signal processing) by estimating the echo path and generating a pseudo-echo signal. Used as an acoustic echo canceler, the MSM7620 cancels the acoustic echo between the loud speaker and the microphone which occurs during hands free communication, such as on a car phone or a conference system phone. Used as a line echo canceler, the device cancels the line echo impedance mismatching in a hybrid. In addition, a quality conversation is made possible by controlling the level and preventing howling with a howling detector, double talk detector, attenuation function and a gain control function, and by controlling the low level noise with a center clipping function. The MSM7620 I/O interface supports m-law PCM. The use of a single chip CODEC, such as the MSM7543, allows the configuration an economic and efficient echo canceler to be configured. Note: If the object is to cancel line echo, the use of the MSM7602 is recommended, for the MSM7602 is provided with a howling detect control pin. In addition, the MSM7602, while having characteristics equivalent to the MSM7620, is packaged small. FEATURES * Handles both acoustic echoes and telephone line echoes. * Cancelable echo delay time: MSM7620-001 ................. For a single chip: 23 ms (max.) MSM7620-011 ................. For a cascade connection (can also be used for a single chip) Master chip: 23 ms (max.) Slave chip: 31 ms (max.) Cancelable up to 213 ms (one master plus six slaves) For a single chip: 23 ms (max.) * Echo attenuation : 30 dB (typ.) * Clock frequency : 18 MHz (36 MHz cannot be used) External input and internal oscillator circuit are provided. * Power supply voltage : 5 V (4.5 V to 5.5 V) * Power consumption : 150 mW (typ.) When powered down: 20 mW (typ.) * Package options: 32-pin plastic SSOP (SSOP32-P-640-0.80-K) (Product name : MSM7620-001GS-K) 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name : MSM7620-011GS-BK) 1/28 Semiconductor MSM7620 BLOCK DIAGRAM MSM7620-001 (Single chip only) RIN S/P Non-linear/ Linear ATT Gain Linear/ Non-linear P/S ROUT Howling Detector Double Talk Detector Power Calculator Adaptive FIR Filter (AFF) - SOUT RST PWDWN P/S Linear/ Non-linear Center Clip ATT + + Non-linear/ Linear S/P SIN WDT VDD VSS Clock Generator X1/CLKIN X2 SCKO MSM7620-011 (Cascade connection or Single chip) RIN S/P Non-Linear /Linear Howling Detector Double Talk Detector SOUT *RST *PWDWN P/S Linear/ Non-linear Clock Generator X1/CLKIN X2 SCKO , Mode Selector I/O Controller INT SYNCO NLP HCL ADP ATT GC IRLD SCK SYNC ATT Gain Linear/ Non-linear P/S ROUT PD15 * PD 0 * OF1 * OF2 * SF1 * SF2 * SIN WDT VDD * VSS * Power Calculator Parallel I/O Port Adaptive FIR Filter (AFF) - Parallel I/O Controller Center Clip ATT + + Non-linear/ Linear S/P Mode Selector I/O Controller INT * SYNCO NLP HCL ADP ATT GC MS IRLD SCK SYNC * * * * If the MSM7620-011 is used in the slave mode, only the diagonally hatched blocks and the pins marked with * are used. 2/28 Semiconductor MSM7620 PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin Plastic SSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin 1 2 3 4 5 6 7 8 Symbol * NLP HCL ADP VSS ATT INT IRLD Pin 9 10 11 12 13 14 15 16 Symbol SIN RIN SCK SYNC SOUT ROUT * VSS Pin 17 18 19 20 21 22 23 24 Symbol * * * X1/CLKIN X2 * PWDWN SYNCO Pin 25 26 27 28 29 30 31 32 Symbol SCKO * RST WDT GC * * VDD *: No connect pin Note: Pin 26 of the MSM7520 is CKSEL, while that of the MSM7620 is in open state. It is possible to replace the MSM7520 with the MSM7620. 3/28 Semiconductor MSM7620 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-Pin Plastic SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol NLP HCL ADP MS ATT INT * IRLD * SIN RIN SCK SYNC SOUT ROUT VSS Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol * * PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 * * Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol PD12 PD13 X1/CLKIN X2 * PWDWN * SYNCO SCKO * * RST WDT GC VDD VDD Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol * * PD14 PD15 * SF2 OF1 * * * SF1 OF2 * VDD * * *: No connect pin Note: Pins 43, 53, and 61 of the MSM7520 are CKSEL, VDD, and TST2 respectively. While these pins of the MSM7620 are in open state, it is possible to replace the MSM7520 with the MSM7620. 4/28 Semiconductor MSM7620 PIN DESCRIPTIONS (1/5) Pin 32-pin 64-pin SSOP 2 QFP 1 Symbol NLP Type I Description The control pin for the center clipping function. This forces the SOUT output to a minimum value (FF) when the SOUT signal is below -54 dBm0. Effective for reducing low-level noise. * Single Chip or Master Chip in a Cascade Connection "H": Center clip ON "L": Center clip OFF * Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 3 2 HCL I The through mode control. When this pin is in the through mode, RIN and SIN data are output to ROUT and SOUT. At the same time, the coefficient of the adaptive FIR filter is cleared. * Single Chip or Master Chip in a Cascade Connection "H": Through mode "L": Normal mode (echo canceler operates) * Slave Chip in a Cascade Connection Same as master This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 4 3 ADP I AFF coefficient control pin. This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets the coefficient to a fixed value, when this pin is configured to be the coefficient fix mode. This pin is used when holding the AFF coefficient which has been once converged. * Single Chip or Master Chip in a Cascade Connection "H": Coefficient fix mode "L": Normal mode (coefficient update) * Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. -- 4 MS I Selection of the Master Chip and slave chip when used in a cascade connection. "L": Single chip or master chip "H": Slave chip 5/28 Semiconductor (2/5) Pin 32-pin 64-pin SSOP 6 QFP 5 ATT I Symbol Type Description MSM7620 Control for the ATT function that prevents howling by attenuators (ATT) for the RIN input and SOUT output. If there is input only to RIN, then the ATT for the SOUT output is activated. If there is no input to SIN, or if there is input to both SIN and RIN, the ATT for the RIN input is activated. Either the ATT for the RIN output or the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is 6 dB. * Single Chip or Master Chip in a Cascade Connection "H": ATT OFF "L": ATT ON "L" is recommended for echo cancellation. * Slave Chip in a Cascade Connection * Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. 7 6 INT I Interrupt signal which starts 1 cycle (8 kHz) of the signal processing. Signal processing starts when H-to-L transition is detected. * Single Chip or Master Chip in a Cascade Connection Connect the IRLD pin. * Slave Chip in a Cascade Connection Connect the IRLD pin of the master chip. INT input is invalid for 100 ms after reset due to initialization. Refer to the control pin connection example. 8 8 IRLD O Load detection signal when the SIN and RIN serial input data is loaded in the internal registers. * Single Chip Connect to the INT pin. * Master Chip in a Cascade Connection Connect to the INT pin of the master chip and all the slave chips. * Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example. 9 10 SIN I Transmit serial data. Input the m-law PCM signal synchronized to SYNC and SCK. Data is read in at the fall of SCK. 6/28 Semiconductor (3/5) Pin 32-pin 64-pin SSOP 10 11 QFP 11 12 RIN SCK I I Receive serial data. Symbol Type Description MSM7620 Input the m-law PCM signal synchronized to SYNC and SCK. Data is read in at the fall of SCK. Clock pin for transmit/receive serial data. This pin uses the external SCK or the SCKO. Input the PCM CODEC transmit/receive clock (64 to 2048 kHz). 12 13 SYNC I Sync signal for transmit/receive serial data. This pin uses the external SYNC or SYNCO. Input the PCM CODEC transmit/receive sync signal (8 kHz). 13 14 SOUT O Transmit serial data. This pin outputs the m-law PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state while there is no data output. 14 15 ROUT O Receive serial data. This pin outputs the m-law PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state while there is no data output. -- -- -- -- -- -- 20 19 30 33 34 51 52 35 PD0 PD11 PD12 PD13 PD14 PD15 X1/CLKIN I/O Bidirectional bus for parallel data transfer between the Master Chip and Slave Chip when used in a cascade connection. The PD15 pin corresponds to MSB. This pin is in a high impedance state while there is no data output. Data is loaded in at the falling edge of SFx. I External input for the basic clock or for the crystal oscillator. Input the basic clock (18 MHz). Refer to the internal clock generator circuit example. 21 36 X2 O Crystal oscilator. Used to configure the oscillation circuit. Refer to the internal clock generator circuit example. When inputting the basic clock externally, insert a 5 pF capacitor with excellent high frequency characteristics between X2 and GND. 23 38 PWDWN I Power-down mode control. "L": Power-down mode "H": Normal operation mode During power-down, all input pins are disabled and output pins are in the following sates : High impedance : SOUT, ROUT, PD0 to 15 "L": SYNCO, SCKO "H": OF1, OF2 Holds the last state : WDT, IRLD Not affected: X2, MCKO Reset after power-down is released. 7/28 Semiconductor (4/5) Pin 32-pin 64-pin SSOP 24 QFP 40 SYNCO O 8 kHz sync signal for the PCM CODEC. Symbol Type Description MSM7620 Connect this pin to the SYNC pin and the PCM CODEC transmit/receive sync pin. Leave it open if using an external SYNC. 25 41 SCKO O Transmit clock signal (200 kHz) for the PCM CODEC. Connect this pin to the SCK pin and the PCM CODEC transmit/receive clock pin. Not affected by reset. Outputs "0" during power-down. Leave it open if using an external SCK. 27 44 RST I Reset signal. "L": Reset mode "H": Normal operation mode During initialization, input signals, except for PWDWN are disabled for 100 ms after reset (after RST is returned from "L" to "H"). Input the basic clock during the reset. Output pins during reset are in the following sates : High impedance: SOUT, ROUT, PD0 to 15 "L": WDT "H": OF1, OF2 Not affected: X2, SYNCO, SCKO, IRLD, MCKO 28 29 45 46 WDT GC O I Test pin. Leave this pin open. Input signal for the gain controller when RIN input is controlled and the RIN input level is controlled and howling is prevented. The gain controller adjusts the RIN input level when it is -20 dBm0 or above. RIN input levels from -20 to -11.5 dBm0 will be suppressed to -20 dBm0 in the attenuation range from 0 to 8.5 dB. RIN input levels above -11.5 dBm0 will always be attenuated by 8.5 dB. * Single Chip or Master Chip in a Cascade Connection "H": Gain control ON "L": Gain control OFF "H" is recommended for echo cancellation. * Slave Chip in a Cascade Connection Fixed at "L" This pin is loaded in synchronization with the falling edge of the INT signal or the rising edge of RST. 8/28 Semiconductor (5/5) Pin 32-pin 64-pin SSOP -- QFP 54 SF2 I Parallel data transfer flag. * Single Chip Fixed at "H" * Master Chip in a Cascade Connection Fixed at "H" * Slave Chip in a Cascade Connection Symbol Type Description MSM7620 Connect OF2 of the master chip to the first stage slave chip. Connect OF1 of the previous stage slave chip to the second and later stage slave chips. Refer to the control pin connection example. -- 55 OF1 O Parallel data transfer flag. * Single Chip Leave this pin open. * Master Chip in a Cascade Connection Connect to the SF1 of all slaves. * Slave chip in a Cascade Connection Connect to the SF2 of the next stage slave chip. Connect the last stage slave chip to the SF1 of the master chip. Refer to the control pin connection example. -- 59 SF1 I Parallel data transfer flag. * Single Chip Connect OF2. * Master Chip in a Cascade Connection Connect OF1 of the last stage slave chip. * Slave Chip in a Cascade Connection Connect OF1 of master chip for all slave chips. Refer to the control pin connection example. -- 60 OF2 O Parallel data output flag. * Single Chip Connect to SF1. * Master Chip in a Cascade Connection Connect to SF2 of the first stage slave chip. * Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example. 9/28 Semiconductor MSM7620 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VIN PD TSTG -- Ta = 25C Condition Rating -0.3 to +7 -0.3 to VDD + 0.3 1 -55 to +150 Unit V V W C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Symbol VDD VSS VIH VIL Ta X1 pin -- -- Condition -- -- Pins other than X1 Min. 4.5 -- 2.4 3.5 0 -40 Typ. 5 0 -- -- -- +25 Max. 5.5 -- VDD VDD 0.8 +85 Unit V V V V V C ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Output High Voltage Output Low Voltage High Level Input Current Symbol VOH VOL IIH Condition IOH = 40 mA IOL = 1.6 mA VIH = VDD VIL = Low Level Input Current IIL VSS to VDD SF1, SF2 with pull-up Input other than the above (Ta = -40C to +85C) Min. 4.2 0 -- -100 -10 -- PD15 to PD0 with pull-up Input other than the above Typ. -- -- 0.1 -50 -0.1 0.1 -50 -0.1 30 4 6 -- -- Max. VDD 0.4 10 -10 -- 10 +10 -- 40 5 8 15 20 Unit V V mA mA mA mA mA mA mA mA mA pF pF High Level Output Current IOZH VOH = VDD VOL = VSS to VDD -100 -10 -- -- -- -- -- Low Level Output Current IOZL Power Supply Current (Operating) Power Supply Current(Stand-by) IDDO -- When extarnal input is used IDDS PWDWN="L" Input Capacitance Output Load Capacitance CI CLOAD as basic clock When oscillation circuit is used as basic clock -- -- 10/28 Semiconductor Echo Canceler Characteristics (Refer to Characteristics Diagram) Parameter Symbol Condition RIN = -10 dBm0 (5 kHz band white noise) Echo Attenuation LRES E. R. L. (echo return loss) = 6 dB TD = 20 ms ATT, GC, NLP: OFF Cancelable Echo Delay Time for a Single Chip or a Master Chip in a Cascade Cancelable Echo Delay Time for a Slave Chip in a Cascade TDS TD RIN = -10 dBm0 (5 kHz band white noise) E.R.L. = 6 dB ATT, GC, NLP: OFF -- -- -- 30 Min. Typ. MSM7620 Max. Unit -- dB -- -- 23 ms 31 ms 11/28 Semiconductor AC Characteristics MSM7620 (Ta = -40C to +85C) Parameter Clock Frequency Clock Cycle Time Clock Duty Ratio Clock "H" Level Pulse Width Clock "L" Level Pulse Width Clock Rise Time Clock Fall Time Sync Clock Output Time Internal Sync Clock Frequency Internal Sync Clock Output Cycle Time Internal Sync Clock Duty Ratio Internal Sync Signal Output Delay Time Symbol fC tMCK tDMC tMCH tMCL tr tf tDCM fCO tCO tDCO tDCC tCYO tWSO Condition -- -- -- -- -- -- -- -- fc = 18 MHz fc = 18 MHz fc = 18 MHz fc = 18 MHz fc = 18 MHz fc = 18 MHz -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 17.5 54.1 40 23.5 23.5 -- -- -- -- -- -- -- -- -- 64 0.488 40 123 45 45 tSCK 45 45 -- -- -- -- -- Typ. 18.0 55.56 50 -- -- -- -- -- 200 5 50 -- 125 tCO -- -- 50 125 -- -- -- -- -- 7tSCK -- tSCK -- -- Max. 18.5 57.1 60 -- -- 5 5 100 -- -- -- 5 -- -- 2048 15.6 60 -- -- -- tCYC-tSCK -- -- -- 138 -- 90 90 Unit MHz ns % ns ns ns ns ns kHz ms % ns ms ms kHz ms % ms ns ns ms ns ns ms ns ms ns Internal Sync Signal Period Internal Sync Signal Output Width Transmit/receive Operation Clock Frequency fSCK Transmit/receive Sync Clock Cycle Time tSCK Transmit/receive Sync Clock Duty Ratio Transmit/receive Sync Signal Period Sync Timing Sync Signal Width Receive Signal Setup Time Receive Data Hold Time Receive Data Input Time IRLD Signal Output Delay Time IRLD Signal Output Width Serial Output Delay Time tDSC tCYC tXS tSX tWSY tDS tDH tID tDIC tWIR tSD tXD 12/28 Semiconductor AC Characteristics (Continued) MSM7620 (Ta = -40C to +85C) Parameter Reset Signal Input Width Reset Start Time Reset End Time Processing Operation Start Time Power Down Start Time Power Down End Time Control Pin Setup Time (INT) Control Pin Hold Time (INT) Control Pin Setup Time (RST) Control Pin Hold Time (RST) Parallel Data Output Signal Width Flag Signal Output Time Flag Signal Output Width Flag Signal Input Width Data Read Setup Time Data Read Hold Time Symbol tWR tDRS tDRE tDIT tDPS tDPE tDTS tDTH tDSR tDHR tWPD tDF tWFO tWFI tFS tFH Condition -- -- -- -- -- -- -- -- -- -- -- -- -- OFz connected to SFx -- -- Min. 1 5 -- 100 -- -- 20 120 20 10 -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- 2tMCK tMCK tMCK/2 tWFO 20 10 Max. -- -- 52 -- 111 15 -- -- -- -- -- -- -- -- -- -- Unit ms ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns 13/28 Semiconductor MSM7620 TIMING DIAGRAM Clock Timing fc. tMCK tDMC X1/CLKIN tDCM SCKO fco. tCO SCKO tDCC SYNCO tWSO tDCC tCYO tDCO tMCH tMCL tr tf Serial Input Timing fsck. tSCK SCK tXS SYNC tDS SIN RIN MSB 7 tWSY tDH 6 5 4 tID IRLD tWIR 3 2 1 tDIC LSB 0 tDIC MSB 7 tSX tCYC tDSC 14/28 Semiconductor Serial Output Timing MSM7620 fsck. tSCK SCK tXS SYNC tSX tCYC tDSC SOUT ROUT Operation Timing After Reset Power Down Timing PWDWN Internal Operation , , ,, tSD tXD tWSY tXD tXD High-Z MSB 7 6 5 4 3 2 1 LSB 0 High-Z tWR RST *Reset timing can be asynchronous tDIT tDRE tDRS Internal operation Reset Initialization *tDPS tDPE Power Down Processing Start *Input MCK in the tDPS interval. MSB 7 Processing Start Note: INT is invalid in the diagonally shaded interval. 15/28 Semiconductor Control Pin Load-in Timing *tCYC INT(IRLD) tDTS NLP, HCL, ATT, ADP, GC tWR RST tDSR NLP, HCL, ATT, ADP, GC tDHR tDTH MSM7620 *Refer to the Serial Input Timing Parallel Output Timing tWPD PD15 PD 0 tDF OF1 OF2 tWFO High-Z Output Data High-Z Parallel Input Timing tWFI SF1 SF2 tFS PD15 PD 0 tFH Input Data - - 16/28 Semiconductor MSM7620 HOW TO USE THE MSM7620 The MSM7620 cancels the echo which returns to SIN using the RIN signal. Connect the base signal to the R-side and the echo generated signal to the S-side. Connection Methods According to Echos Example 1: Canceling acoustic echo (to handle acoustic echo from line input) CODEC ROUT AFF SIN + - MSM7620 RIN Line input m-law SOUT H CODEC Acoustic echo m-law + Example 2: Canceling line echo (to handle line echo from microphone input) CODEC MSM7620 RIN AFF SOUT - ROUT CODEC Microphone Input m-law m-law + SIN Line echo H + Example 3: Canceling line echo in a cascade connection (to handle line echo from microphone input) CODEC MSM7620 RIN Master AFF SOUT - ROUT CODEC Microphone input m-law m-law + SIN H H + Slave AFF PD0 - 15 Line echo 17/28 Semiconductor MSM7620 Example 4: Canceling of both acoustic echo and line echo (to handle both acoustic echo from line input and line echo from microphone input) CODEC ROUT MSM7620 RIN SOUT AFF SIN + - MSM7620 CODEC SIN Line input + - + AFF Acoustic echo m-law m-law ROUT H + SOUT RIN Line echo Microphone input For acoustic echo For line echo 18/28 Semiconductor Control Pin Connection Example Single Chip Connection Two-stage Cascade Connection Master + (slave 1) Master chip MS * * PD15 MS NLP HCL ADP ATT GC PWDWN RST IRLD * OF1 * OF2 +5 V NLP HCL ADP ATT GC PWDWN RST INT SF1 SF2 IRLD OF1 OF2 PD15 +5 V MSM7620 Slave chip MS NLP HCL ADP ATT GC PWDWN RST INT SF1 SF2 IRLD OF1 OF2 PD15 - NLP HCL ADP ATT GC PWDWN RST NLP HCL ADP ATT GC PWDWN RST INT SF1 * +5 V SF2 * - - * PD 0 PD 0 PD 0 Asterisk * mark indicates a pin only for the MSM7620-011. Four-stage Cascade Connection Master + (slave 3) Master chip MS NLP HCL ADP ATT GC PWDWN RST NLP HCL ADP ATT GC PWDWN RST INT SF1 +5 V SF2 IRLD OF1 OF2 PD15 PD 0 +5 V Slave chip 1 MS NLP HCL ADP ATT GC PWDWN RST INT SF1 SF2 IRLD OF1 OF2 PD15 PD 0 +5 V Slave chip 2 MS NLP HCL ADP ATT GC PWDWN RST INT SF1 SF2 IRLD OF1 OF2 PD15 PD 0 +5 V Slave chip 3 MS NLP HCL ADP ATT GC PWDWN RST INT SF1 SF2 IRLD OF1 OF2 PD15 PD 0 - - - - 19/28 Semiconductor Clock Circuit Example Internal clock generator circuit MSM7620 X1/CLKIN R X2 XTAL : 18 MHz R : 1 MW C1 : 27 pF C2 : 27 pF C2 GND MSM7620 C1 GND XTAL External clock input circuit MSM7602 X1/CLKIN X2 18 MHz 5pF GND 20/28 Semiconductor MSM7620 ECHO CANCELER CHARACTERISTICS DIAGRAM ERL vs. echo attenuation 40 30 20 10 0 Echo attenuation [dB] 40 30 20 10 0 RIN input level vs. echo attenuation Echo attenuation [dB] 40 30 20 10 0 -10 -50 -40 -30 -20 -10 RIN input level [dBm] 0 dBm = 2.2 dBm0 Measurement Conditions RIN input: 5 kHz band white noise Echo delay time TD = 20 ms ERL = 6 dB ATT, GC, NLP = OFF 0 ERL. [dB] Measurement Conditions RIN input = -10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) Echo delay time TD = 20 ms ATT, GC, NLP = OFF Echo delay time vs. echo attenuation 30 Echo attenuation [dB] 20 10 0 0 1 50 2 3 100 4 150 5 6 200 7chip Echo delay time [ms] Measurement Conditions RIN input = -10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) ERL = 6 dB ATT, GC, NLP = OFF The second through seventh chips are connected in a cascade. 21/28 Semiconductor Measurement System Block Diagram White noise generator MSM7543 A PCM RIN ROUT MSM7543 PCM A MSM7620 RIN input TD Delay Echo delay time L. P. F. 5 kHz m-law CODEC Level meter MSM7620 m-law CODEC PCM A A PCM SOUT SIN ATT ERL (echo return loss) 22/28 Bidirectional Connection Example APPLICATION CIRCUIT Semiconductor MSM7543GS-VK Mike input C1 SIN ROUT Speaker output R2 R1 R3 1 SG 3 AOUT- 5 PWI 24 SGC R13 C3 + C2 C9 R4 23 6 21 AIN+ VFRO GSX PCMOUT PCMIN BCLOCK 13 12 15 R5 9 14 11 12 7 8 For cancellation of acoustic echo R6 13 10 2 3 4 6 29 R12 For cancellation of line echo 13 10 2 3 4 6 29 MSM7543GS-VK R11 9 14 11 12 7 8 23 27 28 19 TMC 10 PDN SG 1 3 AOUT- PWI 5 24 SGC VDD 9 DG AG 8 16 C10 R10 13 12 15 PCMOUT PCMIN BCLOCK AIN+ VFRO GSX 23 6 21 R8 AIN- 22 R9 SIN ROUT SCK SOUT RIN NLP SOUT RIN NLP SIN ROUT SCK Circuit input C5 RIN SOUT Circuit output 22 AIN- 11 RSYNC 14 XSYNC SYNC INT IRLD PWDWN RST WDT HCL ADP ATT GC HCL ADP ATT GC SYNC INT IRLD PWDWN RST WDT 11 RSYNC 14 XSYNC MSM7620-001GS-K MSM7620-001GS-K R7 PDN 10 23 27 TMC 19 28 8V DD 16 AG DG 9 24 SYNCO 25 SCKO 20 X1 21 X2 32-Pin SSOP VDD VSS VSS 32 C4 5 16 ++ 32 VDD C8 5 VSS 16 VSS 32-Pin SSOP 24 SYNCO 25 SCKO 20 X1 21 X2 C7 + R14 C6 CLK EXT. SCK EXT. SYNC RST PWDWN R1 > 50 kW R2 > 20 kW R3 > 20 kW R4 = 2.2 kW R5 = 10 kW R6 = 10 kW R7 > 50 kW C1 = 0.1 mF C2 = 10 mF C3 = 0.1 mF C4 = 10 mF C5 = 0.1 mF R8 > 20 kW R9 > 20 kW R10 = 2.2 kW R11 = 10 kW R12 = 10 kW R13 = 0-22 W R14 = 0-22 W C6 = 10 mF C7 = 0.1 mF C8 = 10 mF C9 = 1.0 mF C10 = 1.0 mF MSM7620 23/28 R9 R10 Master PCMOUT PCMIN BCLOCK RSYNC VFRO AIN + MSM7543GS-VK R4 Slave MSM7543GS-VK C5 RIN SOUT R7 AIN- R5 C1 SIN PCMOUT ROUT PCMIN 23 AIN + 6 VFRO 21 GSX 23 6 GSX 21 22 R8 1 3 AOUT- 5 SG PWI SGC XSYNC BCLOCK R2 RSYNC Semiconductor R1 44 RST 38 PWDWN 10 PDM 19 TMC 24 VDD 8 22 AIN- 44 RST 38 PWDWN XSYNC 13 12 15 11 14 10 SIN 15 ROUT 12 SCK 13 SYNC R6 10 SIN 15 ROUT 12 SCK 13 SYNC 13 12 15 11 14 R3 Cascade Connection Example 1 SG 3 AOUT- 5 PWI PDM 10 19 TMC 24 SGC R12 C3 + 8V DD 9 DG C7 R12 AG C2 C9 16 MSM7620-011GS-BK MSM7620-011GS-BK AG DG 9 1 2 3 4 5 46 NLP HCL ADP MS ATT GC 41 SCKO 40 SYNCO 35 X1 NLP HCL ADP MS ATT GC 41 SCKO 40 SYNCO 35 X1 1 2 3 4 5 46 16 C10 + C6 C4 + + C8 36 X2 47 VDD 48 VDD 62 VDD SOUT RIN PD15 PD14 PD13 PD12 PD11 PD10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 OF2 SF2 OF1 SF1 INT IRLD 36 X2 47 VDD 48 VDD 62 VDD WDT 45 45 WDT 64-Pin QFP VSS 16 14 11 52 51 34 33 30 29 28 27 26 25 24 23 22 21 20 19 60 54 55 59 6 8 SOUT RIN PD15 PD14 PD13 PD12 PD11 PD10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 OF2 SF2 OF1 SF1 INT IRLD 14 11 52 51 34 33 30 29 28 27 26 25 24 23 22 21 20 19 60 54 55 59 6 8 16 VSS 64-Pin QFP CLK R1 > 50 kW R2 > 20 kW R3 > 20 kW R4 = 2.2 kW R5 = 10 kW R6 > 50 kW C1 = 0.1 mF C2 = 10 mF C3 = 0.1 mF C4 = 10 mF C5 = 0.1 mF R7 > 20 kW R8 > 20 kW R9 = 2.2 kW R10 = 10 kW R11 = 0-22 W R12 = 0-22 W C6 = 10 mF C7 = 0.1 mF C8 = 10 mF C9 = 1.0 mF C10 = 1.0 mF MSM7620 24/28 RST PWDWN Semiconductor MSM7620 NOTES ON USE 1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be amplified, the echo can not be eliminated. Refer to the characteristics diagram for ERL vs. echo attenuation quantity. 2. Set the level of the analog input so that the PCM CODEC does not overflow. 3. The recommended input level is -10 to -20 dBm0. Refer to the characteristics diagram for the RIN input level vs. echo attenuation quantity. 4. Applying the tone signal to this echo canceler will decrease echo attenuation. If the tone signal is input to the SIN pin during the time that a signal is input to the RIN pin, this echo cancceler operates faultily. A signal must be input to either the RIN pin or the SIN pin. The ADP or HCL pin must be driven at "H" if the tone signal is input to the SIN pin during the time that a signal is input to the RIN pin. 5. For changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. Perform a reset to make it converge. If the state of the echo path changes after a reset, convergence may again be difficult. In cases such as a change in the echo path, perform a reset when possible. 6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock simultaneouly with power ON. If powering down immediately after power ON, be sure first input 10 or more clocks of the basic clock. 7. After powering ON, be sure to reset. 8. After the power down pin is changed to a "1" from a "0", be sure to reset. 9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 dB. 25/28 Semiconductor MSM7620 EXPLANATION OF TERMS This function prevents howling and controls the noise level with an attenuator for the RIN input and SOUT output. Refer to the explanation of pins (ATT pin). Echo Attenuation : If there is talking (input only to RIN) in the path of a rising echo arises, the echo attenuation refers to the difference in the echo return loss (canceled amount) when the echo canceler is not used and when it is used. Echo attenuation = (SOUT level during through mode operation) - (SOUT level during echo canceler operation) [dB] Echo Delay Time : This is the time from when the signal is output from ROUT until it returns to SIN as an echo or other similar device. Acoustic Echo : When using a hands free phone, and so on, the signal output from the speaker echoes and is input again to the microphone. The return signal is referred to as acoustic echo. Telephone Line Echo : This is a signal which is delayed midway in a telephone line and returns as an echo, due to reasons such as a hybrid impedance mismatch. Gain Control Function : This function prevents howling and controls the sound level by with a gain controller for the RIN input. Refer to the explanation of pins (GC pin). Center Clipping Function : This function forces the SOUT output to a minimum value when the signal is below -57 dBm0. Refer to the explanation of pins (NLP pin). Double Talk Detection : Double talk refers to a state in which the SIN and RIN signals are input simultaneously. In a double talk state, a signal outside the echo signal which is to be canceled can be input to the SIN input, resulting in misoperation. The double talk detector prevents such misoperations of the canceler. Howling Detection : This is the oscillating state caused by the acoustic coupling between the loud speaker and the microphone during hands free talking. Howling not only interferes with talking, but can also cause misoperation of the echo canceler. The howling detector prevents such misoperation and prevents howling. Echo Return Loss (ERL) : When the signal output from ROUT returns to SIN as an echo, ERL refers to how much loss there is in the signal level during ROUT. ERL = (ROUT level) - (SIN level of the ROUT signal which returns as an echo) [dB] If ERL is positive (ROUT > SIN), the system is an attenuator system. If ERL is negative (ROUT < SIN), the system is an amplifier system. Attenuating Function : 26/28 Semiconductor MSM7620 PACKAGE DIMENSIONS (Unit : mm) SSOP32-P-640-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.83 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/28 Semiconductor MSM7620 (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 28/28 |
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